To better understand the impact of the Entity List export controls on Huawei, we need to take a look at the critical parts of the integrated circuit (IC) value chain. In this post, I’ll discuss the development of electronic design automation (EDA) tools for chip design. The software-based EDA industry is a recent phenomenon. Today’s dominant EDA vendors were all founded in the 1980s: Mentor Graphics (1981), Cadence (1987/1988), and Synopsys (1987). Before the 1980s, computer-aided design (CAD) functions were typically sold with their requisite hardware, workstations. Much of the earlier CAD work was done inside systems companies. For example, IBM was a systems company par excellence as it made both chips and the end products the chips went into, such as mainframe computers. Today there are EDA tools to cover the whole design process, usually referred to as the design flow.
Three things happened in the 1980s to create the software-based EDA industry we know. First, technological advances to develop software tools across all the important design functions proceeded apace so one could have a suite of EDA tools to cover the entire design flow. Second, the rise of general-task, powerful workstations allowed software-only EDA firms to gain a competitive edge. Third, standardization of EDA tools allowed them to gain wider acceptance in the commercial marketplace.
In the 1990s, a fourth development that spurred the EDA industry was the maturation of pure-play foundries making chips for fabless design firms. Neither the foundries nor the fabless design firms were going to spend the money required to develop in-house EDA tools, as larger firms such as IBM had done in the past. Consequently, fabless design firms relied on EDA vendors for their design tools, and the EDA firms began to work closely with the foundries to ensure that the EDA software could create fabrication-ready designs.
The pace of innovation in IC design is so rapid and occurs across such an array of chip products that two features of the industry have emerged. Just to attempt to keep pace, the two largest vendors, Cadence and Synopsys, routinely spend 30 percent or more of their revenues on R&D each year. Consequently, the EDA industry has not yet developed one dominant platform for design and instead has an oligopoly of three large players. Indeed, it is not uncommon for different design teams within the same firm to use EDA tools from different vendors. Some go so far as to argue that each of the “Big Three” EDA vendors offers a superior tool in one specific segment of the design flow.1 Consequently, best practice is to use tools from all three vendors. Nevertheless, switching costs for entirely replacing one firm’s EDA tools with another’s appear high, so market shares have been fairly stable across the Big Three.2
The other feature is that acquiring new technology from start-ups is very common despite the Big Three remaining the dominant firms for three decades. The increasing amount of overall semiconductor R&D spending taken up by EDA firms (15.1% to 15.9% between 2016-2018) and the ability of venture-backed start-ups to take on higher-risk projects means these new firms make attractive targets for acquisition; at the same time, they find it difficult to compete with the established triumvirate. In other words, the start-ups can offer a particular advanced tool for a certain design task, but because these start-ups typically do not produce wider sets of tools, they have a very narrow competitive position. As a result, their best strategy more often than not is simply to sell themselves to one of the dominant firms.3 The Big Three have consistently captured two-thirds of the EDA market broadly defined over time. Since all three firms are based in America (Germany’s Siemens acquired Mentor in 2017) and their EDA technology is overwhelmingly of American origin, these firms’ EDA tools fall firmly under the Entity List export controls.
In the next post, I will discuss how the Huawei sanctions will impact Huawei’s chip design, global EDA firms and the local Chinese EDA industry.
 To give some examples, Synopsys is regarded as having the best compiler, Cadence the best layout tools, and Mentor the best verification tools.
 One reason switching costs may be high is simply the fact that designers can grow comfortable with tools from one provider and getting down the learning curve with another company’s tools may appear formidably inefficient at the team if not individual level.
 Henkel, Ronde, and Wagner, “Entrepreneurship as a Contest.”